1. Field
Embodiments of the present invention generally relate to methods for forming vertically stacked nanowires with desired materials on a semiconductor substrate, and more particularly to methods for forming vertically stacked nanowires on a semiconductor substrate with desired materials for field effect transistor (FET) semiconductor manufacturing applications.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 25 nm and 20 nm dimensions and beyond, whereas the thickness of the dielectric layers remain substantially constant, with the result of increasing the aspect ratios of the features. Furthermore, reduced channel length often causes significant short channel effect with conventional planar MOSFET architecture. In order to enable fabrication of next generation devices and structures, three dimensional (3D) device structure is often utilized to improve performance of the transistors. In particular, fin field effect transistors (FinFET) are often utilized to enhance device performance. FinFET devices typically include semiconductor fins with high aspect ratios in which the channel and source/drain regions for the transistor are formed thereover. A gate electrode is then formed over and along side of a portion of the fin devices utilizing the advantage of the increased surface area of the channel and source/drain regions to produce faster, more reliable and better-controlled semiconductor transistor devices. Further advantages of FinFETs include reducing the short channel effect and providing higher current flow. Device structures with hGAA configurations often provide superior electrostatic control by surrounding gate to suppress short channel effect and associated leakage current.
In some applications, horizontal gate-all-around (hGAA) structures are utilized for next generation semiconductor device applications. The hGAA device structure includes several lattice matched channels (e.g., nanowires) suspended in a stacked configuration and connected by source/drain regions.
In hGAA structures, different materials are often utilized to form the channel structures (e.g., nanowires), which may undesirably increase the manufacturing difficulty in integrating all these materials in the nanowire structures without deteriorating the device performance. For example, one of the challenges associated with hGAA structures include the existence of large parasitic capacitance between the metal gate and source/drain. Improper management of such parasitic capacitance may result in much degraded device performance.
Thus, there is a need for improved methods for forming channel structures for hGAA device structures on a substrate with good profile and dimension control.